Basic Computer Organization and Design

Instruction Codes and the Control Unit

Adapted from Figure 5-6, Computer System Architecture, Third Edition by M. Morris Mano, 1993, Prentice Hall.

Control signals are connected to the appropriate registers and ALU. Decoding of the IR in conjunction with timing signals T₀…T₁₅ produce control signals causing register and ALU operation.

SC ¬ 0 //clear sequence counter to 0 activating the timing signal T₀.

The sequence counter is incremented or cleared synchronously. For example the combination, D₃T₄: SC ¬ 0, synchronously clearing the sequence counter to 0.

Instruction Cycle   Basic Computer Register Figure

Fetch places the contents of PC onto the bus by making bus selection inputs S₂S₁S₀ = 010, then transfers the contents of the bus to AR by enabling the LD input of AR. This is accomplished during timing signal T₀. During timing signal T₁, fetch places the contents of AR selected memory onto the bus by making selection inputs S₂S₁S₀ = 111, then transfers the content of the bus to IR by enabling the LD input of IR, and increments PC by enabling the INR of PC.

Decode occurs during timing signal T₂, at which time the contents of the instruction register are passed to the I flip-flop IR(15), a 3x8 decoder IR(12-14), and to the address register IR(0-11). We use simple register transfer statements to represent all of these actions as follows:

1. Fetch
   T₀: AR ¬ PC
   T₁: IR ¬ M[AR], PC ¬ PC + 1
2. Decode
   T₂: D₀,…, D₇ ¬ Decode IR(12-14), AR ¬ IR(0-11), I ¬ IR(15)
3. Read the effective address from memory if the instruction has an indirect address (T₃:). Instruction Formats
• Memory Reference (D₇')
• Direct (I') effective address is already in AR, perform Execute at T₃.
• Indirect (I), T₃: AR ¬ M[AR]
• Register Reference or Input/Output (D₇)
• Register (I') perform Execute at T₃
• I/O (I) perform Execute at T₃
4. Execute T₃ or T₄:

The cycle continues from 4 back to 1 to fetch, decode, and execute until a HALT instruction is encountered.

Once a general understanding of the control unit's function is acquired, one can abstract away from these details and concentrate on the register transfer level of operation. The control unit continuously cycles the CPU through the fetch, decode, and execute cycle.

Software to Implement a Logic Instruction

The internal organization of a computer is defined by the sequence of microoperations it performs on the data stored in its registers. The basic computer has four machine instructions that perform logic operations: AND, CMA, LDA, and CLA. Note that the OR operation is not a basic computer machine instruction. This instruction will be implemented by software applying DeMorgan's Law. Consider the following table that implements the OR operation:

Address (Hex)	Binary Instruction Code (Hex)	Symbolic Instruction	Register Transfer Statements /remarks
100	2109	LDA A	DR ¬ M[AR] AC ¬ DR, SC ¬ 0
101	7200	CMA	AC ¬ (AC)'
102	3300	STA	M[AR] ¬ AC, SC ¬ 0
103	210A	LDA B	DR ¬ M[AR] AC ¬ DR, SC ¬ 0
104	7200	CMA	AC ¬ (AC)' /complement B
105	0300	AND	DR ¬ M[AR] AC¬ ACÙ DR, SC¬ 0 /AND with A' ® A'Ù B'
106	7200	CMA	AC ¬ (AC)' /complement again to get AÚ B
107	3301	STA	M[AR] ¬ AC, SC ¬ 0
108	7001	HALT	S ¬ 0 /Halt computer
109	0202	operand A
10A	2020	operand B
300	FDFD	operand A'
301	2222	operand A Ú B