Basic Computer Control Cycle Microoperations

Control Cycle Step	Control Signal	Microoperations
Fetch	R'T0: R'T1:	AR¬ PC IR¬ M[AR], PC¬ PC+1
Decode	R'T2:	D0..D7¬ Decode IR(12..14), AR¬ IR(0..11), I¬ I(15)
Indirect (only if the instruction has an indirect address)	D'7I T3:	AR¬ M[AR]
Execute
In the basic computer, the above control cycle repeats continuously, starting again on SC¬ 0 that concludes each execute until the HLT command is executed causing S¬ 0.
Interrupt
T0T1T2(IEN)(FGI + FGO):			R¬ 1
	RT0: RT1: RT2:	AR¬ 0, TR¬ PC M[AR]¬ TR, PC¬ 0 PC¬ PC+1, IEN¬ 0, R¬ 0, SC¬ 0

Adapted from Table 5-6, Computer System Architecture, Third Edition by M. Morris Mano, 1993, Prentice Hall.