CPU Simulation—Fetch
Due: See Schedule
CSC 242
Objectives:
To understand the activity that occurs on a
computer's data path by
simulating the register transfer, ALU, memory transfer, and control operations
of a simple CPU. The first phase of this exercise will involve writing class
definitions for registers in the CPU and storage in memory. In addition, number format
conversions and state displays will be developed. The efficacy of the routines
will be demonstrated by implementing the Fetch phase of the instruction cycle
for a simple CPU.
Tasks:
You will begin the CPU simulation by implementing the Fetch phase of the instruction cycle for the semantics provided on page 159 of your text. Notice that there are only two lines of semantic activity associated with the Fetch phase:
R'T0: AR <= PC
R'T1: IR <= M[AR], PC<= PC +1.
However, these two lines of semantic activity imply several supporting structures must be present.
1. There must be three registers: the AR, IR, and PC. The three registers must possess abilities including the capacities to load and increment contents. You will also need to be able to clear (set the value of each bit to "0") registers. Further, the registers have differing sizes and your simulation must preserve the fact that the AR and the PC are 12-bit registers, while the IR (and later the AC, DR, and TR) is a 16-bit register. Your simulation must preserve and display the contents of each CPU register in binary and hexadecimal. Decimal is optional. Register contents must be formatted for a consistent display within right justified fields.
2. There must be a simulated memory M containing 4096 cells, each capable of storing a string containing four hexadecimal digits. These digits represent the 16-bit content of each of the 4096 cells. You will need to be able to initialize the memory cells and to display the content of any cell when it changes. For initialization, assume that the simulated memory contents will be stored in a text file. The initialization phase of the simulator must open and read values from this file. The data format in the text file will include two strings for each memory cell. The first, a three-digit string, will represent the memory address. The second, a four-digit string will use characters to represent the content of memory at the given address. For example, one line of the text file might contain the string "0F3 90AB"; this means that memory location 0F3 should be assigned the value 90AB; in brief, M[0F3] <= 90AB.
3.
Implement and demonstrate the fetch phase of the
instruction cycle by showing the register state after fetching one instance of
each instruction in the instruction set. Note: The register state display should show the last value in the AR,
the instruction in the IR and the PC pointing to the location of the next
instruction. One copy of the instruction segment of memory should also be
printed. The display should show the content of the registers in a labeled,
legible format. In particular, you must separate nybbles with a space,
right-align register content displays, and show only as many nybbles as the
register actually holds.
4. The initialization process must load memory from a file. It must also initialize the PC based on a value from the file. Third, the Fetch/Execute cycle must be started. For this phase, test files will include (a) a count of the number of lines of memory data, (b) the initial value for the PC, and (c) the memory data. Notice that as the simulation advances, the AR changes, the PC advances but remains one step ahead of the AR, the IR consecutively receives the values from the memory. A memory dump showing the contents of modified cells must be included.
5. The simulator must keep track of CPU time. Each time the Fetch phase is completed, two clock cycles must be added to the CPU clock time. Thus, in order to Fetch exactly one instance of each instruction in the instruction set, how many clock cycles will elapse?
Sample output after
loading memory and fetching one instruction.