CPU Simulation-Execute 2
Due: See Schedule
CSC 242

Objectives:

To simulate the register transfer, ALU, and control operations of a simple CPU. This is the fourth and final phase of the CPU simulation exercise and it extends the fetch, decode and execute phases of the assignment so that input and output instructions can be executed. In addition, support for a simple interrupt mechanism is to be implemented to accept and process input requests only.

Tasks:

1. Implement the semantics for each instruction whose high order nybble is "F." This set includes both the input/output instructions (INP and OUT) and the flag checking instructions SKI and SKO. It also includes the interrupt control instructions ION and IOF.

 2. Implement the semantics for transferring control to the interrupt handler distributed in class. The semantics of the transfer of control are:

RT₀: AR¬ 0, TR¬ PC
RT₁: M[AR]¬ TR, PC¬ 0
RT₂: PC¬ PC+1, IEN¬ 0, R¬ 0.

2. Incorporate the interrupt handler in the initialization of your simulated computer. In addition, you must add a procedure that will decide whether or not to accept or to defer a request for service from a device. You will need to queue unaccepted requests so that they can served as execution allows.

3. You will test your simulation using the script below. The format of the script contains a clock cycle during which the input device requests service and the hexadecimal representation of a byte of information (this byte is the new content for the input register INPR). You may test using a script containing either the input bytes D1, 2F, and CE or the bytes A3, B4, and C5. In either case, use the arrival times indicated below.

Time	Input Character
23	D1 or A3
36	2F or B4
70	CE or C5

4. Use the files CPUTest13.dat and CPUTest14.dat to test your simulator. You may also use out13.txt and out14.txt for verification.