CPU Simulation—Decode Pseudocode
Due: See Schedule 
CSC 242

To simulate the register transfer, ALU, and control operations of a simple CPU. DECODE is the second phase of the CPU simulation exercise. The goal of the FETCH assignment in the simulator was to get an instruction to execute retrieved from the memory M and stored in the CPU special purpose register known as the instruction register, denoted IR. Once an instruction is stored in the IR and before the semantic activity that it represents can be conducted, the control unit, CU, must account for and interpret each bit. The process of interpreting the pattern of bits in the IR is called decoding the instruction. By decoding instructions, you are simulating one of the core functions of the control unit.

In addition, you will augment your simulator display and CPU to include certain flags, which are storage elements that hold the results of various parsings or computations. The one-bit flags that are required for DECODE are the "run" flag "S" and the "indirect" flag "I".  (Other flags include and extended carry flag E, interrupts enabled IEN, input available FGI and output ready FGO, but these are not required for the DECODE phase of the assignment.)  You will need a storage component D capable of storing integer values in the range [0, ..., 7].

2. Be sure to update the clock correctly. In particular, setting I, D, and the AR from IR[11..0] adds one clock cycle to the total. If the instruction is a memory-referencing indirect instruction, an additional clock cycle is required for the indirect step in which AR receives the lower order three nybbles of M[AR], in symbols AR<=M[AR][11..0]. Notice that for some instructions the decode step takes only one clock cycle and for other instructions it takes two clock cycles. The time for decoding depends upon the semantic activities of the particular instruction.

3. Display the contents of the PC, AR, and IR registers in the CPU, the cells of memory M that are currently being used, the value of D, and the status of both the I and S flags. When displaying the state of the machine, you must use both binary and hexadecimal representations of the values stored in each register. In addition, hexadecimal representations of the contents of each memory cell that is used must be displayed to show the initial and final contents of memory. When displaying the CPU state, you must output the name of the instruction in the IR and identify whether it is a memory-referencing, a register-referencing, or an I/O instruction. In addition, if the instruction is memory referencing, you must indicate the addressing mode, direct or indirect.

4. Develop the stub methods that will be used when the instruction semantics are actually implemented. Include stub methods for each type of instruction (ADD, AND, etc.). Currently, the only function of these stubs is to report the specific instruction's name. You will need to create a validation process similar to validRegisterInstruction  as an active error trap when D = 7 in order to ensure that only valid register-referencing (when D=7 and I=0) or I/O (when D=7 and I=1) instructions are presented. 

5. In the CPU showState method, if you didn't replace the Morse Code for the FETCH exercise, append your name to the memory dump. Demonstrate the FETCH and DECODE phases of the instruction cycle by showing the register state after fetching and decoding one instance of each instruction in the instruction set: CPUTestDecode1. Also test your code on CPUTestDecode2, and CPUTestDecode3. Turn in your tested output by email and/or demonstrate your simulator in person. The first test set tests general parsing activity. The second test exercises indirect memory references. Finally, the third file verifies whether your simulator traps an illegal instruction bit pattern.

6. Control the FETCH, DECODE, EXECUTE, CFI, and showState loop using the S flag. The initialization method should set S=1. The loop should iterate while S=1. The HLT instruction should set S=0, and consequently, stop the instruction-cycle loop and terminate the simulation.