****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 0 Recently modified memory cells Cell Contents 100 0123 101 1234 102 2345 103 3456 104 4567 105 5678 106 6789 107 89AB 108 9ABC 109 ABCD 10a BCDE 10b CDEF 10c DEF0 10d EF01 10e 7800 10f 7400 110 7200 111 7100 112 7080 113 7040 114 7020 115 7010 116 7008 117 7004 118 7002 119 F800 11a F400 11b F200 11c F100 11d F080 11e F040 11f 7001 9ab 1234 abc 5678 bcd 9ABC cde DEF0 def 3456 ef0 789A f01 BCDE Flags S=1 I=0 D=0 E=0 R=0 IEN=0 FGI=0 FGO=0 PC => 100 0001 0000 0000 256 ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 3 Flags S=1 I=0 D=0 E=0 R=0 IEN=0 FGI=0 FGO=0 AR => 123 0001 0010 0011 291 PC => 101 0001 0000 0001 257 IR =>0123 0000 0001 0010 0011 291 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => 00 0000 0000 0 OUTR => 00 0000 0000 0 AND instruction memory referencing--direct addressing mode ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 6 Flags S=1 I=0 D=1 E=0 R=0 IEN=0 FGI=0 FGO=0 AR => 234 0010 0011 0100 564 PC => 102 0001 0000 0010 258 IR =>1234 0001 0010 0011 0100 4660 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => 00 0000 0000 0 OUTR => 00 0000 0000 0 ADD instruction memory referencing--direct addressing mode ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 9 Flags S=1 I=0 D=2 E=0 R=0 IEN=0 FGI=0 FGO=0 AR => 345 0011 0100 0101 837 PC => 103 0001 0000 0011 259 IR =>2345 0010 0011 0100 0101 9029 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => 00 0000 0000 0 OUTR => 00 0000 0000 0 LDA instruction memory referencing--direct addressing mode ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 12 Flags S=1 I=0 D=3 E=0 R=0 IEN=0 FGI=0 FGO=0 AR => 456 0100 0101 0110 1110 PC => 104 0001 0000 0100 260 IR =>3456 0011 0100 0101 0110 13398 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => 00 0000 0000 0 OUTR => 00 0000 0000 0 STA instruction memory referencing--direct addressing mode ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 15 Flags S=1 I=0 D=4 E=0 R=0 IEN=0 FGI=0 FGO=0 AR => 567 0101 0110 0111 1383 PC => 105 0001 0000 0101 261 IR =>4567 0100 0101 0110 0111 17767 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => 00 0000 0000 0 OUTR => 00 0000 0000 0 BUN instruction memory referencing--direct addressing mode ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 18 Flags S=1 I=0 D=5 E=0 R=0 IEN=0 FGI=0 FGO=0 AR => 678 0110 0111 1000 1656 PC => 106 0001 0000 0110 262 IR =>5678 0101 0110 0111 1000 22136 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => 00 0000 0000 0 OUTR => 00 0000 0000 0 BSA instruction memory referencing--direct addressing mode ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 21 Flags S=1 I=0 D=6 E=0 R=0 IEN=0 FGI=0 FGO=0 AR => 789 0111 1000 1001 1929 PC => 107 0001 0000 0111 263 IR =>6789 0110 0111 1000 1001 26505 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => 00 0000 0000 0 OUTR => 00 0000 0000 0 ISZ instruction memory referencing--direct addressing mode ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 25 Flags S=1 I=1 D=0 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => 234 0010 0011 0100 564 PC => 108 0001 0000 1000 264 IR =>89AB 1000 1001 1010 1011 -30293 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 AND instruction memory referencing--indirect addressing mode ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 29 Flags S=1 I=1 D=1 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => 678 0110 0111 1000 1656 PC => 109 0001 0000 1001 265 IR =>9ABC 1001 1010 1011 1100 -25924 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 ADD instruction memory referencing--indirect addressing mode ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 33 Flags S=1 I=1 D=2 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => ABC 1010 1011 1100 2748 PC => 10A 0001 0000 1010 266 IR =>ABCD 1010 1011 1100 1101 -21555 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 LDA instruction memory referencing--indirect addressing mode ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 37 Flags S=1 I=1 D=3 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => EF0 1110 1111 0000 3824 PC => 10B 0001 0000 1011 267 IR =>BCDE 1011 1100 1101 1110 -17186 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 STA instruction memory referencing--indirect addressing mode ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 41 Flags S=1 I=1 D=4 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => 456 0100 0101 0110 1110 PC => 10C 0001 0000 1100 268 IR =>CDEF 1100 1101 1110 1111 -12817 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 BUN instruction memory referencing--indirect addressing mode ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 45 Flags S=1 I=1 D=5 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => 89A 1000 1001 1010 2202 PC => 10D 0001 0000 1101 269 IR =>DEF0 1101 1110 1111 0000 -8464 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 BSA instruction memory referencing--indirect addressing mode ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 49 Flags S=1 I=1 D=6 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => CDE 1100 1101 1110 3294 PC => 10E 0001 0000 1110 270 IR =>EF01 1110 1111 0000 0001 -4351 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 ISZ instruction memory referencing--indirect addressing mode ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 52 Flags S=1 I=0 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => 800 1000 0000 0000 2048 PC => 10F 0001 0000 1111 271 IR =>7800 0111 1000 0000 0000 30720 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 CLA instruction register type ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 55 Flags S=1 I=0 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => 400 0100 0000 0000 1024 PC => 110 0001 0001 0000 272 IR =>7400 0111 0100 0000 0000 29696 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 CLE instruction register type ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 58 Flags S=1 I=0 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => 200 0010 0000 0000 512 PC => 111 0001 0001 0001 273 IR =>7200 0111 0010 0000 0000 29184 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 CMA instruction register type ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 61 Flags S=1 I=0 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => 100 0001 0000 0000 256 PC => 112 0001 0001 0010 274 IR =>7100 0111 0001 0000 0000 28928 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 CME instruction register type ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 64 Flags S=1 I=0 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => 080 0000 1000 0000 128 PC => 113 0001 0001 0011 275 IR =>7080 0111 0000 1000 0000 28800 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 CIR instruction register type ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 67 Flags S=1 I=0 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => 040 0000 0100 0000 64 PC => 114 0001 0001 0100 276 IR =>7040 0111 0000 0100 0000 28736 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 CIL instruction register type ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 70 Flags S=1 I=0 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => 020 0000 0010 0000 32 PC => 115 0001 0001 0101 277 IR =>7020 0111 0000 0010 0000 28704 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 INC instruction register type ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 73 Flags S=1 I=0 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => 010 0000 0001 0000 16 PC => 116 0001 0001 0110 278 IR =>7010 0111 0000 0001 0000 28688 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 SPA instruction register type ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 76 Flags S=1 I=0 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => 008 0000 0000 1000 8 PC => 117 0001 0001 0111 279 IR =>7008 0111 0000 0000 1000 28680 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 SNA instruction register type ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 79 Flags S=1 I=0 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => 004 0000 0000 0100 4 PC => 118 0001 0001 1000 280 IR =>7004 0111 0000 0000 0100 28676 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 SZA instruction register type ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 82 Flags S=1 I=0 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => 002 0000 0000 0010 2 PC => 119 0001 0001 1001 281 IR =>7002 0111 0000 0000 0010 28674 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 SZE instruction register type ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 85 Flags S=1 I=1 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => 800 1000 0000 0000 2048 PC => 11A 0001 0001 1010 282 IR =>F800 1111 1000 0000 0000 -2048 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 INP instruction I/O type ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 88 Flags S=1 I=1 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => 400 0100 0000 0000 1024 PC => 11B 0001 0001 1011 283 IR =>F400 1111 0100 0000 0000 -3072 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 OUT instruction I/O type ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 91 Flags S=1 I=1 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => 200 0010 0000 0000 512 PC => 11C 0001 0001 1100 284 IR =>F200 1111 0010 0000 0000 -3584 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 SKI instruction I/O type ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 94 Flags S=1 I=1 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => 100 0001 0000 0000 256 PC => 11D 0001 0001 1101 285 IR =>F100 1111 0001 0000 0000 -3840 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 SKO instruction I/O type ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 97 Flags S=1 I=1 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => 080 0000 1000 0000 128 PC => 11E 0001 0001 1110 286 IR =>F080 1111 0000 1000 0000 -3968 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 ION instruction I/O type ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 100 Flags S=1 I=1 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => 040 0000 0100 0000 64 PC => 11F 0001 0001 1111 287 IR =>F040 1111 0000 0100 0000 -4032 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 IOF instruction I/O type ****.- ..-. ....- ...- -...****** Mano CPU state at time Clock cycle = 103 Flags S=0 I=0 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0 AR => 001 0000 0000 0001 1 PC => 120 0001 0010 0000 288 IR =>7001 0111 0000 0000 0001 28673 DR =>0000 0000 0000 0000 0000 0 AC =>0000 0000 0000 0000 0000 0 TR =>0000 0000 0000 0000 0000 0 INPR => A3 1010 0011 163 OUTR => 00 0000 0000 0 HLT instruction register type ****.- ..-. ....- ...- -...****** Memory dump follows: Cell Contents 100 0123 101 1234 102 2345 103 3456 104 4567 105 5678 106 6789 107 89AB 108 9ABC 109 ABCD 10a BCDE 10b CDEF 10c DEF0 10d EF01 10e 7800 10f 7400 110 7200 111 7100 112 7080 113 7040 114 7020 115 7010 116 7008 117 7004 118 7002 119 F800 11a F400 11b F200 11c F100 11d F080 11e F040 9ab 1234 abc 5678 bcd 9ABC cde DEF0 def 3456 ef0 789A f01 BCDE