Basic Computer Registers Connected to a Common Bus

Adapted from Figure 5-4, Computer System Architecture, Third Edition by M. Morris Mano, 1993, Prentice Hall.

Note that the content of any register can be applied onto the bus and an operation can be performed in the arithmetic logic unit (ALU) circuit during the same clock cycle. The same clock cycle transfers the content of the bus into the designated destination register and the output of the ALU into AC.

Consider S2 S1 S0 = 100, with LD of DR enabled, the contents of AC transfer to DR while the contents of DR transfer to AC via the ALU.

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