Adapted from Figure 5-6, Computer System Architecture, Third Edition by M. Morris Mano, 1993, Prentice Hall.

The 3 x 8 decoder translates the operation code of the IR into signals D₀ … D₇, the high bit of the IR is transferred to the I flip-flop, and bits 0 … 11 of the IR are transferred directly to the control logic gates.

The 4 x 16 decoder translates the 4 bits (representing 0 … 15) from the sequence counter into timing signals T₀ … T₁₅. The sequence controller continuously counts from 0 to 15 based on the increment (INR) signal but can be synchronously cleared to 0 if at time T₄ decoder output D₃ is active.

Adapted from Figure 5-7, Computer System Architecture, Third Edition by M. Morris Mano, 1993, Prentice Hall.