1  Description of Project/Activity

The proposed project involves development of a "Design and Test Platform for Embedded Digital Signal Processing Systems".

1.1  Introduction to Digital Signal Processing

Signals are patterns of variation of physical quantities such as temperature, pressure, voltage, brightness, etc. Most real-world signals are analog in nature, which means that they vary continuously in time and in amplitude. Signals are processed to extract information from them. This information normally exists in the form of signal amplitude, frequency or spectral content, phase, or timing relationships with respect to other signals. Though analog signals can be processed using analog hardware there are some advantages to digital signal processing:
(a). Analog hardware is usually limited to linear operations whereas digital hardware can implement arbitrary nonlinear operations. (b). Digital hardware is programmable, which allows for easy modification of the signal processing procedure, both on-line and off-line. (c). Digital hardware is less sensitive than analog hardware to variations in ambience variables, such as temperature, etc.

These advantages translate into lower cost and are the main reason for the ongoing shift from analog to digital processing in wireless telephones, consumer electronics, industrial controllers, and numerous other applications.

In order to store, transmit, or process analog signals using digital hardware, first analog signals must be converted into a digital signals by sampling and quantization. In this respect, the term digital signals refers to signals that have been conditioned and formatted into digits. Examples of digital signals include data transmitted over local area network (LANs) or other high-speed networks. Digital Signal Processors (DSPs) are found in a wide range of applications such as in communications, servo and motor control, speech and video processing. Today, DSPs are used in ECG (electro cardiogram) monitors, Fax, modems, cellular phones, digital answering machines, feature phones, and digital cameras to name just a few.

1.2  Digital Signal Processing System

Typically, in a Digital Signal Processing system, the analog signal is converted into binary form by a device known as analog-to-digital converter (ADC). The output of the ADC is a binary representation of the analog signal and is manipulated arithmetically by Digital Signal Processor (DSP) in much the same way as manipulating numbers. After processing, the signal may be converted back into analog form using a digital-to-analog converter (DAC). The core of a Digital Processing System is a DSP. The factor that distinguishes DSPs from general purpose microprocessors, such as Intel Pentium or Sun SPARC processor, is their speed and efficiency in performing functions specific to digital signal processing in real time. This speed advantage is achieved by support of digital processing functions, such as filtering, Fast Fourier Transform (FFT), and data compression within the processor instruction architecture.

A complete signal processing system usually consists of several components for signal conditioning and incorporates multiple signal processing techniques. In some cases, for example, it may be desirable to reformat the information contained in a signal. This would be the case in the transmission of voice signal over a frequency division multiple access (FDMA) telephone system. In this case, analog techniques are used to ßtack" voice channels in the frequency spectrum for transmission via microwave relay, coaxial cable, or fiber.

In other cases, the signal containing the information is buried in noise, and the primary objective may be the signal recovery. Techniques such as filtering, auto-correlation, and convolution, are often used to accomplish this type of processing.

Yet another requirement for signal processing may be to compress the frequency content of the signal (without losing significant information) and then format and transmit the information at lower data rates, thereby achieving a reduction in required channel bandwidth. High speed modems and adaptive pulse code modulation systems (ADPCM) make extensive use of data reduction algorithms, as do mobile radio systems, MPEG recording and playback, and High Definition Television (HDTV).

1.3  Digital Signal Processing in the Computer Science Discipline

Recent shift from analog to digital signal processing combined with the availability of high level programming tools [1] for DSPs has presented special opportunity for computer scientists to participate in the exciting field of embedded systems development.

Topics in digital signal processing [2], [3] include a number of specific techniques. These techniques can be roughly categorized into two families:

  1. Signal-analysis/feature-extraction techniques aim to extract useful information from a given signal. Examples include speaker and speech recognition, location and identification of targets from radar and sonar signals, detection and characterization of abrupt changes in meteorological, seismographic or econometric data.
  2. Signal filtering/shaping techniques aim to improve the quality of a given signal, sometimes as a preliminary step before analysis or feature extraction. Examples include the removal of noise and interference by frequency selective or statistical filtering, splitting of a signal into simpler components, time-domain and frequency domain averaging, deconvolution and deblurring.

A Digital Signal Processing platform provides an economical way to introduce algorithms and techniques for real-time digital signal processing to computer science students. In a typical development environment, the platform is connected to a host computer thru a parallel port. Once the program is compiled, linked, debugged simulated and tuned for performance it is loaded on to the DSP with the emulator software. From thereon the module functions as an embedded signal processing system.

1.4  How the funds from the Cahill Grant will be used

Thru the Motorola University Program, I have obtained the core hardware components for building a design and test platform. The main hardware components include (i) a Motorola DSP56824 16-bit processor, and (ii) coder-decoder chip for conversion of voice signal to digital signal. On the software side, I have obtained from Metroworks Inc. an Integrated Development Environment (IDE). The IDE software includes: C language compiler, linker, loader, debugger, simulator, and emulator tools for the DSP56824 processor. The software is, however, provided for a trial period of one month. Using the software environment IDE, I have successfully programmed the DSP56824 signal processor for filtering out background noise from voice signals.

The funds from Cayhill award will be used (i) to purchase the IDE software when the trial period expires in November 2000, for continued development of more applications in voice processing and (ii) to add real-time video processing capabilities.

After several applications in audio and video processing are successfully built with the design platform, a grant proposal will be submitted to NSF during Fall 2001 to fund the establishment of a Digital Signal Processing Laboratory (DSP Lab). The DSP Lab will be used to support research and instruction in the fast growing fields of embedded systems, image processing, and voice processing.

1.5  References

1. Novel Digital Signal Processing Architecture with Microcontroller Features, White Paper, Motorola 1999.
2. Rulph Chassaing Digital Siganl Processing, Laboratory Experiments Using C and the TMS320C31 DSK, 1999.
3. Mixed-Signal and DSP Deisgn Techniques, Analog Devices 2000.

2  Budget

SN Software, Hardware Vendor Price
1.Integrated Development Environment (IDE) Metroworks CodeWarrior200.00
2. Charged Couple Device (CCD) Camera Analog Devices 450.00
3. Video Encoder, and Decoder Analog Devices250.00
4. Video Processing Software libraries Hyperception 2500.00
5. Video Monitor Analog Devices 250.00
Total* 3650.00

*The Computer Science Department has agreed to provide matching funds for up to $ 1000.00 towards the cost of this project.

3   Qualifications of the Applicant

I have participated in the following workshops on topics in Digital Signal Processing, and Field Programmable Gate Arrays. I have also published paper in VLSI (very large integrated circuit) conference: Workshop on Parallel Algorithms and VLSI Architectures.
(1) Digital Signal Processing workshop, Organized by Texas Instruments, October 7, 2000 Research Triangle Park
(2) Mixed-Signal and DSP Design Techniques, Organized by Analog Devices, September 27, 2000 Research Triangle Park
(3) 8-bit MCU Solutions from Motorola, Organized by Motorola, May 9, 2000 Research Triangle Park
(4) National Science Foundation Workshop for Undergraduate Faculty Enhancement on ``Integerated Engineering Workstation'', August 8-12 1994, Bucknell University, Lewisburg, PA.
(5) National Science Foundation workshop for Undergraduate Faculty Enhancement on ``Logic Synthesis'', June 21-25 1993, Mississipi State University, MS.
(6) National Science Foundation workshop for Undergraduate Faculty Enhancement on ``Workshop on Microelectronics Systems Education'', July 12-23 1993, Boston University, Boston, MA.

4   Curriculum Vitae

I. Publications:

  1. "Domination in Bounded Interval-Tolerance Graphs",
    ICPADS-2000, International Conference on Parallel and Distributed Systems, July 2000, Japan.

  2. ``Parallel Algorithms for k-tree recognition and its applications'',
    HICSS-27, 27th Hawaii International Conference on System Sciences, 1994. jointly with Shietung Peng.

  3. ``Mixed Domination in trees- A Parallel Algorithm'',
    Congressus Numerantium, vol. 100-104, 1994, jointly with Shietung Peng.

  4. ``Parallel Algorithms for Finding Connected, Independent, and Total Domination in Interval Graphs'', Parallel Algorithms and VLSI Architectures, June 1991, Elsevier Publications, jointly with Shietung Peng.

  5. ``Parallel Algorithms for Cographs and Parity Graphs with Applications'', Journal of Algorithms, Vol. 11, 1990, pp 252-284, jointly with Shietung Peng.

  6. ``Parallel Algorithm for Maximum Matching in Cographs,''
    Congressus Numerantium, Vol.77, December 1990, pp 217-227, jointly with Shietung Peng.

  7. ``Parallel Algorithm for Cographs: Recognition and Applications'',
    Springer Verlag Series- Lecture Notes in Computer Science, 1989, jointly with Shietung Peng.

  8. ``Parallel Algorithms for Complement Reducible Graphs and Parity Graphs'',
    Proceedings of the International Conference on Computing and Information, May 1989, jointly with Shietung Peng.

  9. ``Parallel Algorithms for Path Covering, Hamiltonian Paths, Hamiltonian Cycles Cograph'', 1990 International Conference on Parallel Processing, Vol.3 1990, 364-365, jointly with Shietung Peng.

II. Invited Lectures :

0.
``Parallel Algorithms for K-trees and its Applications'', Invited lecture at the Computer Science Department, University of Umea, Sweden, Feb. 28 1994.
``Parallel Algorithms for Finding Connected, Independent, and Total Domination in Interval Graphs'', at the workshop on Parallel Algorithms and VLSI Architectures, June 3-6 1991, France.
``Parallel Algorithm for Maximum Matching in Cographs,'' at the Twenty-first Southeastern International Conference on Combinatorics, Graph Theory and Computing, Florida Atlantic University, February 12-16, 1990.
``Parallel Algorithm for Cographs: Recognition and Applications'', at Algorithms and Data Structures Workshop WADS'89 Ottawa, Canada, August 16-18 1989.
International Conference on Computing and Information, Toronto, May 23-27 1989.

III. Membership in professional societies:

0.

ACM Association for Computing Machinery (1986-present)
IEEE Computer Society (1986-present)
DECUS -Digital Equipment Corporation Users Society (1984-present)
MUG - MOSIS Users Group (1990 -present)
Upsilon Pi Epsilon - National Computer Science Honor Society (1991-present)

File translated from TEX by TTH, version 2.25.
On 13 Dec 2000, 22:21.